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SynaptiCAD upgrades Waveformer Lite tool
SynaptiCAD has released an upgrade to Waveformer Lite, its entry-level tool for generating VHDL and Verilog test benches graphically from timing diagrams drawn by the user.
Verilogger Extreme adds encrypted IP model support
Synapti CAD has updated Verilogger Extreme, a compiled-code Verilog simulation and debugging environment that adds support for encrypted IP models from all major ASIC/FPGA vendors.
SynaptiCAD launches 64bit simulation environment
SynaptiCAD has released a 64bit Linux version of Verilogger Extreme, a Verilog simulation and debug environment.
SynaptiCAD to give away free simulator licences
SynaptiCAD will be giving away free six-month licences for its Verilogger Extreme compiled-code Verilog 2001 simulator for a limited time.
SynaptiCAD updates timing diagram editors
SynaptiCAD has introduced version 14 of its timing diagram editors: Waveformer Pro, Timing Diagrammer Pro and Data Sheet Pro.
