PXI module supports JTAG/Boundary Scan Test

The PXI5396-FXT was developed in cooperation with Selex Galileo and supports both the structural JTAG/Boundary Scan Test and dynamic I/O operations up to 100MHz for the execution of functional tests in critical environments.

The PXI 5396/FXT-x is a two-component solution and consists of a PXI-supported Interface Module (IFM) and an offset Core Module (CM).

The distance of the modules can be up to 2m without loss of performance.

The Core Module is equipped with a front connector by Virginia Panel, which allows the module to be inserted directly in the interface of the Interchangeable Test Adaptor (ITA).

Due to this, an optimum reliability of the I/O signals is achieved even with fixtures offset from the PXI chassis.

Two variants are available, which differ in the depth of the on-board memory (72MB with the PXI 5396/FXT and 144MB with the PXI 5396/FXT-XM).

Both variants provide 96 single-ended channels, configurable as input, output and tri-state, which allow simultaneous driving and measuring, as well as real-time comparison.

While the signals are processed synchronously to the test bus operations in the JTAG mode, the dynamic I/O mode allows functional testing with freely programmable clock rates within the range of 500Hz to 100MHz.

Normally, structural Boundary Scan tests are carried out first with functional tests following.

For the flexible adaptation to the Unit Under Test (UUT), the I/O are programmable from 1.8V to 5V, and allow individual pull/up and pull/down adjustments for each channel.

Additional features are included for the safety of the interface, improved current efficiency and the impedance adjustment.

Up to five PXI 5396/FXT-x modules can be cascaded in an I/O brick, with all PXI trigger signals supported for synchronisations.

The implemented Variocore technique adds flexibility to the module by enabling the use of custom IP embedded in the hardware of the module.

The PXI 5396/FXT-x devices are supported by the integrated JTAG/Boundary Scan development environment System Cascon starting from version 4.5, which relieves the user from the time-consuming manual editing of the project data.

This includes the automatic generation of wiring diagrams, as well as the Automatic Test Program Generation (ATPG) for Boundary Scan.

After the test is finished a failure diagnosis is carried out on the pin and net level, with the fault location being visualised in the layout.

The execution of functional dynamic tests and the subsequent failure diagnosis are based on the support of the standard IEEE 1445 Digital Test Interchange Format (DTIF), which is now integrated in System Cascon.

Additional to the import processors, an interactive waveform editor is also available.