Econa ARM-based processors are energy efficient

The single- and dual-core ARM SoC processors are said to enable high performance, while reducing power and cost for next-generation gateways, storage and consumer electronics devices.

The integrated Econa CNS3XXX processors are said to feature a rich set of integrated hardware accelerators and a range of I/Os for glueless voice, video and data connectivity.

Power-management techniques enable the devices to deliver low-power operation starting at less than 1W.

The devices target applications including FTTH broadband gateways, network attached storage appliances, multimedia picture frames, media and print servers, IP cameras and wireless access points.

At the heart of the Econa CNS3XXX devices is an integrated power-management unit that enables a total of six different power-saving modes during operation, including: wake-on-LAN support; dynamic control of CPU power-per-core; and automatic shutdown of non-operational logic.

On-chip voltage regulators enhance the effectiveness of this PMU, enabling power consumption figures ranging from less than 1W for the single-core version to less than 2.5W for the highest-end dual-core version.

Devices in the Cavium Econa CNS3XXX family are built around high-performance ARM11 MPcore processors and caches including Superscalar, ARM11 MPcore processors operating at up to 700MHz, each with 32KB I-cache, 32KB D-cache and a large 256KB L2 cache to provide more than 1,400 Dhrystone MIPS (DMIPS).

Each ARM11 MPcore processor comes with instruction set extensions for digital signal processing (DSP) and media processing, and integrates a vector floating point unit (VFP) and memory management unit (MMU).

The cores also incorporate ARM's Jazelle technology, which enhances the performance of Java applets running on the CNS3XXX family.

The high-performance cores combined with large caches deliver non-blocking, wire-speed performance for voice, video and data applications.

DSP extensions on the ARM11 MPcore processors drive enhanced voice applications including support for wideband codecs, DECT and advanced call-control features such as conferencing.

Additional features of the SoC processors include: advanced acceleration engines, which include a packet switch for wire-speed switching; hardware-based NAT and QoS engine; TCP offload; packet processing engine (PPE) for wire-speed packet processing; content inspection engine for L7 application processing and filtering, Raid 5/6 XOR engine, 2D graphics engine with an integrated LCD controller, and a security engine for high-performance IPSec, SSL, intrusion prevention and anti-virus processing.

The devices also support acceleration for the popular standards-compliant video codecs.

High-bandwidth, low-latency integrated memory, system and networking interfaces provided by the Econa CNS3XXX family include: intelligent x16/x32-bit, 800MHz DDR2 memory controller; three Ethernet MAC interfaces supporting RGMII/GMII/MII, Dual USB2.0/SATA2/PCIe - all with integrated PHYs; TDM/PCM LCD interface; SDIO camera interface and system interfaces including GPIO, SPI, UART, I2S and I2C.

The Econa CNS3XXX software development kit (SDK) builds upon Cavium's existing Octeon and Octeon Plus SDK and includes: Linux SMP; GNU Toolchain; Simple Executive for fast path applications; performance tools; simulator; feature rich APIs for hardware acceleration; and reference applications.