Lattice announces reference clock for Serdes
Lattice Semiconductor
IspClock5400D reference clock solution
Lattice Semiconductor and Epson Toyocom have announced a low-cost reference clock solution for Serdes applications.
By utilising Lattice's IspClock5400D device and the appropriate SG-710ECK CMOS oscillator from Epson Toyocom, a designer has a low-cost reference clock for Serdes applications such as XAUI or SDI Video.
With this solution, Serdes-based designs no longer require an LVDS or LVPECL high-frequency oscillator.
Lattice's IspClock5400D device has a low phase noise, on-chip PLL that generates these higher clock frequencies.
This high frequency is generated by multiplying an Epson Toyocom low-cost, lower frequency CMOS oscillator.
The IspClock5400D device accepts the oscillator's CMOS input.
This input is then multiplied up to the appropriate frequency for the Serdes reference clock rate.
The solution is available for Serdes reference clock frequencies such as 156.25, 270 and 312.50MHz.
The programmable output interface of the IspClock5400D device can drive multiple differential interface requirements such as LVDS or LVPECL.
IspClock5400D evaluation boards are available.
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