Toshiba develops three circuit techniques for embedded SRAM operating at low voltages
Toshiba Electronics
Circuit techniques for embedded SRAM
Toshiba has developed three circuit techniques for embedded SRAM that it says will contribute to lower power consumption by electronic devices.
Toshiba has manufactured a 40nm 2Mb SRAM test chip that uses the developed techniques to ensure that SRAM can be operated properly even when the voltage is low.
According to the company, the circuit removes the need to program the wordline level voltage chip by chip and reduces the cell failure rate to one-hundredth of that of conventional SRAM. Additionally, controlling the wordline voltage allows the voltage characteristics of the control circuit to match the slowest cell’s voltage characteristics.
The circuits can operate within a supply voltage range of 0.5–1.0V and, at 0.5V power consumption is 57 per cent lower than that of conventional SRAM.
Toshiba is currently accelerating the development of the techniques and hopes to apply them to semiconductors capable of operating within a wide voltage range.
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