Talus-based reference flow for SoC designs

The reference flow has been developed for system-on-chip (SoC) designs that incorporate high-performance embedded microprocessor cores from MIPS Technologies, including the MIPS32 1004K, 74K, 34K and 24K ranges.

Using the Talus-based reference flow with these cores, MIPS's and Magma's mutual customers can accelerate the design and delivery of SoC devices.

With the new reference flow and the MIPS IP, mutual customers can achieve repeatable results and speed the deployment of advanced SoCs.

Based on Talus 1.1, the latest release of Magma's IC implementation system, the flow leverages the Talus Design synthesis tool's enhanced clock tree synthesis and the Talus Core technology, which performs timing optimisation concurrently during routing.

These advanced capabilities allow designers to quickly achieve timing closure.

In addition, synthesis results using these reference flows for Talus 1.1 show performance improvements of as much as seven per cent when compared with results using Talus 1.0.

Premal Buch, general manager of Magma's Design Implementation business unit, said: 'Successful SoC implementation is dependent on having reliable IP and a proven flow.

'By incorporating advanced capabilities into Talus 1.1, such as early clock tree modelling, advanced crosstalk optimisation, concurrent optimisation during routing and providing reference flows, Magma is equipping designers with the technology they need for silicon success,' added Buch.