TSMC adopts Synopsys's HSIM circuit simulator

The HSIM simulator will be deployed for TSMC advanced SRAM compilers for timing, power simulation, dynamic infrared (IR) drop and EM analysis, as well as for full-chip simulation with extracted package models.

Using the latest version of the HSIM tool, TSMC is able to improve memory characterisation throughput by 10 times while achieving tight correlation to silicon measurements.

ST Juang, senior director of design infrastructure marketing at TSMC, said: 'At 40nm nodes and beyond, post-layout parasitic data, power reliability and leakage need to be accounted for when characterising memories.

'We had adopted HSIM for our memory IP characterisation at previous technology nodes and, after extensive evaluation, we chose HSIM for our sub-40nm flow based on its advanced technologies for post-layout analysis and its ability to deliver accurate simulation results while maintaining fast throughput for our largest-memory compilers.' As layout geometries shrink, the accurate characterisation of memories becomes more of a challenge.

Previous methodologies that have employed critical path and cut netlists are no longer adequate to accurately verify the impact of cross-coupling effects and layout parasitics.

As a result, more customers have adopted the method of verifying the entire memory design, including the chip packaging, for sub-40nm process nodes.

HSIM is claimed to address this challenge by delivering accurate simulation results with superior performance.

It provides a solution for circuit simulation, post-layout analysis, reliability analysis and electrical rule checking.