Tensilica provides design-flow support for DPUs
Tensilica
Xtensa 8 DPUs
Tensilica provides out-of-the-box automated design-flow support for key technologies within Synopsys' Galaxy Implementation Platform.
This includes DC Ultra RTL synthesis and IC Compiler place and route for Tensilica's Xtensa 8 and Xtensa LX3 dataplane processors (DPUs).
This latest design flow provides up to 15 per cent improvement in processor speed, area and power, in addition to faster design closure over previous Synopsys-based design flows.
Tensilica delivers scripting support to help customers exploit advanced technologies provided by Synopsys' Galaxy platform, including Topographical technology, congestion-driven placement, pin-placement optimisation, useful skew and Zroute, which collectively provide high frequency with area-efficient layout.
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