Serial IP core supports RapidIO 2.1 specification
Altera
RapidIO IP core
Altera has announced the first intellectual property (IP) core supporting the RapidIO 2.1 specification.
Altera's Serial RapidIO IP core supports up to four lanes at 5.0GBaud per lane, addressing the increased bandwidth and reliability needs of the wireless and military markets.
The IP core is optimised for Stratix IV FPGAs with embedded transceivers and is supported within Quartus II software v9.1.
The RapidIO 2.1 specification enables increased performance up to 20GBaud in applications ranging from next-generation wireless base stations, high-performance military systems and DSP farms.
Support for the RapidIO 2.1 specification builds upon Altera's complete Serial RapidIO solution, which includes an end-point IP core that is backward compatible to the RapidIO 1.3 specification, reference designs, application notes, testbenches and interoperability reports with leading digital signal processor and switch vendors.
The Serial RapidIO IP core has been qualified against the RapidIO Trade Association's bus functional model and is supported within Altera's 40nm Stratix IV GX and Stratix IV GT FPGAs and Hardcopy IV GX ASICs.
The Serial RapidIO IP solution is part of Altera's Megacore IP library and is available now for evaluation upon download and installation of Quartus II software v9.1.
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