PCI Express RC Lite supports bridging functions

Using a low-cost programmable FPGA platform, designers can implement the specific bridge function that matches the interface available on their particular host CPU.

Designers will also have the flexibility to implement multiple bridges or different configurations of bridges in a single FPGA, reducing the number of components on the board.

Lattice's PCI Express RC Lite solution is supported by Lattice's IP Express FPGA design tool module.

Included as a standard feature in the Lattice Diamond design environment, the IP Express module reduces design time by allowing IP parameterisation and timing analysis on the designer's desktop.

This allows users to customise Lattice's library of IP functions for their applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis, prior to making any IP purchase commitments.

An FPGA-based PCI Express RC Lite solution provides system designers with a flexible way to support intelligent bridging functions between today's high-performance ASSPs that support only the serial PCI Express host interface and legacy CPU parallel host interfaces.

Users may choose to maintain support for legacy CPUs due to legacy code compatibility, and/or because the CPU has been qualified for markets such as military, satellite or industrial.

The PCI Express RC Lite IP core provides a x1 or x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in the PCI express protocol stack.

The PCI Express 1.1 x1 RC Lite IP core requires approximately 4,500 FPGA look-up tables (LUTs) in 16-bit mode.

The PCI Express 1.1 x4 RC Lite IP core requires approximately 10,500 FPGA LUTs in 64-bit mode.