LSI launches link layer processor SoC
LSI
Link layer processor system-on-chip
LSI Corporation has announced its next-generation link layer processor (LLP), a new addition to the company's family of multi-service processors.
A single line card design, the LLP system-on-chip (SoC) supports all major protocols and is scalable across the bandwidth spectrum from T1/E1 to STM-1, meaning that a single OEM development effort can now be leveraged across all major services and performance levels.
Until now, telecom OEMs had to purchase and integrate individual cards for each major service type.
The LSI LLP runs on a common, highly-scalable hardware and software platform, reducing both development time and the number of cards needed to provide multiple network services.
OEMs are now able to leverage a single design effort across multiple applications such as wireless base stations, wireless transport and high-end radio network controllers.
In wireless applications, the LLP SoC supports backhaul of both BTS (2G) and Node B (3G) traffic to BSC (2G) and RNC (3G).
Similarly, the new multi-core LLP enables the transport of multiple legacy protocols across wireline packet networks.
Network uptime is maximised because the LLP continues to operate WAN modules in the event of system reboot and switches automatically to back-up capacity if a system failure occurs that would otherwise impact traffic.
The result is an efficient, available network capable of delivering multiple, any-to-any services.
The LLP SoC provides a range of multi-service support including Metro Ethernet, IP, MPLS, edge-to-edge pseudo-wire emulation (PWE3) using CESoPSN, SAToP, ATM, TC/IMA, HDLC/MLPPP, AAL1, frame relay and Transcoder Rate Adaptation Unit protocols.
More stories
LSI adds processor core and memory blocks to range
LSI has announced the addition of the multicore-capable PowerPC 476 microprocessor core and high-speed, embedded DRAM memory blocks to its portfolio of custom silicon intellectual property (IP).
LSI unveils Ultramapper II system-on-chip
LSI has introduced the Ultramapper II, an addition to its family of multi-service processors for radio network controllers, base station controllers and customer premise equipment (CPE) applications.
LSI launches chipset for IP connections
LSI has unveiled a system-powered, silicon data access arrangement-based foreign exchange office chipset that enables connections between IP applications and conventional analogue lines.
LSI announces echo cancellation software
LSI Corporation has announced echo cancellation software for the LSI Starpro range of multicore media processors.
Sercos supplies single-chip controllers for use with simple Sercos III slave devices
Sercos has released the Sercos Easyslave single-chip controller, which can be used with simple Sercos III slave devices and supports cycle times as low as 31.25usec.
