Lattice and Praesum release RapidIO 2.1 IP core
Lattice Semiconductor
RapidIO 2.1 IP core
Lattice Semiconductor and Praesum Communications have announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA range.
The core supports 1x, 2x and 4x lane configurations at up to 3.125Gbps lane speeds, offering a low cost, low-power programmable SRIO solution.
Lattice has also licensed this IP core from Praesum and has full rights to use and sub-license it.
RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing.
In the past, vendors had to rely on expensive, premium FPGAs for these applications.
However, the combination of the Serial RapidIO 2.1 core and the LatticeECP3 FPGA will allow customers to develop low-power infrastructure solutions for 3G, LTE and Wimax without sacrificing performance or cost.
The Serial RapidIO 2.1 core and other Lattice IP cores such as low latency CPRI and GbE/SGMII comprise a comprehensive IP suite in support of wireless-infrastructure applications.
Praesum's small-footprint Serial RapidIO 2.1 IP core can be used for processor bridging, control-plane interfaces and bridging to legacy interfaces.
The core architecture for the Serial RapidIO 2.1 IP core includes the following features: it provides infrastructure support for external logical layer functions, enabling maximum flexibility; it provides a choice of logical layer functions that are important for the application; it provides a choice of how logic-layer functions interact with the rest of the system - SOC bus or streaming interfaces; it supports software implementations of control-plane oriented functions such as doorbells and messages; and it is backwards compatible with the v1.3 specification.
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