IP core is targeted for low-power applications
Evatronix
C65C02 microprocessor IP core
Evatronix's C65C02 65C02 compatible microprocessor IP core complies with the original 6502 Instruction Set Architecture by MOS Technology and is targeted for low-power applications.
A list of smart improvements makes the core better suited for non-obsolete uses, while retaining compatibility with all the industry-certified software should the IP be used as a direct 6502 or 65C02 chip replacement.
The most significant feature of the 65C02 architecture is the introduction of two additional instructions for efficient power management - STP for processor halt and WAI for wait for interrupt.
These instructions also decrease overall interrupt latency and enable synchronisation with external events.
Significant optimisation was implemented in opcodes.
These were documented and instructions that can push or pull X and Y index registers to/from the stack were introduced.
Undefined opcodes were converted into NOPs (no operation performed).
The 65C02 ISA addresses and fixes numerous problems with system flags and is said to significantly increase the usefulness of decimal mode.
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