IP core implements wide set of peripherals

The C80186EC implements a DRAM refresh unit, three timers/counters, two UARTs, four DMA engines, three 8-bit I/Os, two 8259-compatible components and a watchdog.

For much smaller CPU overhead, the C80186EC can be used with the C80187 math coprocessor IP core from Evatronix, a component designed to aid floating point operations.

The C80186EC was developed with the Personal Hardware Modeler (PHM).

The PHM was employed for the functional reverse engineering that is usually required to overcome ambiguities of the original documentation and to implement undocumented features.

It also enables the developed IP to be thoroughly checked against full original chip functionality covering all corner cases not only in RTL simulation but also in hardware supported co-simulation with utilisation of an FPGA prototype.

The C80186EC has joined a broad line of other Evatronix IP cores equivalent to obsolete chips that cover the following processors: 8-bit Zilog Z80, 16-bit Motorola 68000, Intel 80187 numeric coprocessor as well as clones of the digital signal processors once manufactured by Texas Instruments (32025) and Motorola (56000).

The cores have been used in numerous projects in application areas such as telecommunication, military electronics and industrial automation.

As with all other Evatronix IP cores, these cores are technology independent and therefore can be implemented in any ASIC or FPGA designs.

The C80186EC microcontroller is available for licensing now.

The IP core is delivered as a VHDL or Verilog source code with a set of scripts and macros for simulation/synthesis support.