I2S-SC controller introduces TDM mechanism
Evatronix
I2S-SC controller IP
Evatronix has introduced the I2S-SC controller IP, which is compatible with the Philips I2S specification and all its modes.
The I2S-SC reduces the number of supported channels from eight to one and introduces the Time Division Multiplexing (TDM) mechanism for more efficient multi-channel handling.
The controller features more than a dozen configurable parameters that let the user further adjust the IP to his application needs.
The most significant options are: serial clock and word select polarities, audio channel width, data delay, the size of external Fifo and the sample bits order.
For easy implementation into a variety of system bus interfaces, the I2S-SC features the universal OCP socket and a set of wrappers for the most common bus architectures: AHB, OPB and PLB.
More stories
HSIC technology delivers low power consumption
Evatronix has announced the introduction of a High-Speed Inter-Chip (HSIC) compatible PHY IP for power and area savings in USB 2.0 chip-to-chip connections.
Web application demonstrates IP core capabilities
Evatronix has introduced an online application that demonstrates the capabilities of the company's JPEG 2000 Encoder IP core for SoC designers.
IP core is targeted for low-power applications
Evatronix's C65C02 65C02 compatible microprocessor IP core complies with the original 6502 Instruction Set Architecture by MOS Technology and is targeted for low-power applications.
Driver improves Nand Flash application development
Evatronix has introduced the latest release of the software driver for its Nand Flash memory controller IP core.
IP core implements wide set of peripherals
Evatronix has released the 80186EC IP core - a 16-bit microprocessor compatible with the 80c186ec chip from Intel and can address a variety of possible applications.
