HSIC technology delivers low power consumption
Evatronix
High-Speed Inter-Chip (HSIC) compatible PHY IP
Evatronix has announced the introduction of a High-Speed Inter-Chip (HSIC) compatible PHY IP for power and area savings in USB 2.0 chip-to-chip connections.
Implementation of the HSIC technology enables setting up a direct connection on a PCB board between a USB Host chip and other on-board USB devices.
The HSIC standard has low power consumption thanks to the elimination of requirements to support long external USB cables while remaining USB protocol compliant and therefore USB-software compatible.
Being straightforward to use with all USB software gives HSIC an advantage over other inter-chip connection standards such as I2C.
Through the implementation of a 240MHz DDR interface the HSIC standard provides full support for the 480Mbps data transfer of the USB protocol.
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