Evatronix offers Display-CTRL controller
Evatronix
Display-CTRL controller
Evatronix SA, a provider of silicon intellectual property (IP), has released the Display-CTRL: a high-resolution display controller IP core for PC, home video, mobile and industrial applications.
The controller supports all common display formats from QVGA to WUXGA and full HD resolutions.
Grzegorz Potok, IP core developer, said: 'Our display controller has been designed to support a wide range of AMBA AHB-based video application system-on-chips.
'With the variety of available interfaces and resolutions, the Display-CTRL is a perfect solution for an SoC design where visual experience matters,' he added.
The controller accepts RGB 24 or 15 bits per pixel input colour formats and features a complete set of programmable horizontal and vertical timing parameters - front porch, back porch and sync intervals.
For seamless system bus integration, the core is delivered with a native AMBA AHB bus master/slave interface and a programmable FIFO controller.
Both depth and near-full level parameters for the FIFO are configurable, as is the endianess of the interface.
The Display-CTRL IP core has been extensively tested for compliance with VESA and EIA/CEA standards (HD resolutions).
When working in 1,920 x 1,200 resolution with 60Hz refresh rate, the controller reaches a speed of 154MHz.
ADV7120 and AD9889B from Analog Devices and CH7301C from Chrontel have been used for Display-CTRL hardware verification.
For HDMI connection, Display-CTRL's external interface matches the ST7887 from Sitronix.
The Display-CTRL controller is now available for licensing, according to the company.
The IP core is delivered as a Verilog source code with a set of scripts and macros for simulation/synthesis support.
An optional reference design for a proprietary evaluation board facilitates application development.
More stories
HSIC technology delivers low power consumption
Evatronix has announced the introduction of a High-Speed Inter-Chip (HSIC) compatible PHY IP for power and area savings in USB 2.0 chip-to-chip connections.
Web application demonstrates IP core capabilities
Evatronix has introduced an online application that demonstrates the capabilities of the company's JPEG 2000 Encoder IP core for SoC designers.
IP core is targeted for low-power applications
Evatronix's C65C02 65C02 compatible microprocessor IP core complies with the original 6502 Instruction Set Architecture by MOS Technology and is targeted for low-power applications.
I2S-SC controller introduces TDM mechanism
Evatronix has introduced the I2S-SC controller IP, which is compatible with the Philips I2S specification and all its modes.
Driver improves Nand Flash application development
Evatronix has introduced the latest release of the software driver for its Nand Flash memory controller IP core.


