EFEC IP cores designed for 100G applications
Altera
EFEC7/EFEC20 multi-dimensional IP cores
Altera has announced availability of what it claims are the industry's first integrated, enhanced forward error correction (EFEC) IP cores optimised for Stratix IV and Stratix V series FPGAs.
The EFEC7 and EFEC20 are multi-dimensional IP cores developed by Altera's Newfoundland Technology Centre and specifically designed for 100G applications such as metro and long-haul optical transport networks (OTN).
Altera's EFEC IP cores provide the required performance and error free delivery over longer distances.
Altera's EFEC7 and EFEC20 are ultra-high gain, hard-decision FEC cores that enhance 100G networks and provide the smallest FPGA-based EFEC implementation available in the industry today, according to the company.
The EFEC7 and EFEC20 leverage a Streaming Turbo Product Code BCH code (SPC-BCH) for claimed best-in-class gain at the standard G.709.
At seven and 20 per cent overhead ratio respectively, the EFECs provide increased transmission distance and lower transmission power.
Altera's SPC-BCH EFECs efficiently solve the implementation complexity issues associated with 100G data rates.
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