Driver improves Nand Flash application development
Evatronix
IP core software driver
Evatronix has introduced the latest release of the software driver for its Nand Flash memory controller IP core.
The driver supports all functionalities of the controller and introduces features to facilitate Nand Flash application development.
The Evatronix Nand Flash memory controller software driver is written entirely in ANSI C for operating system independence.
It natively supports memories from manufacturers such as Numonyx, Samsung, Micron and Toshiba, but with a unified set of commands it can be configured to support custom memory chips.
The latest release of the driver features a set of configurable options for best fit to customer's application.
These options include support for implementation of an indirect DMA buffer, DMA and Bad Block Scan modules, as well as for configurable system clock frequencies.
The release also allows software configuration of hardware ECC (Error Correction Code) settings.
The Evatronix Nand Flash memory controller provides support for single- and multi-level cell memories and for high-speed Nand Flash memories that reach up to 200 MT/s.
The controller is compatible with the Onfi 2.2 specification for compatibility with Micron and Numonyx memory chips and features support for memories from other manufacturers.
The controller features an internal OCP socket for implementation into any system bus.
A set of wrappers for AMBA AHB, OPB, PLB, Avalon and Flexbus system buses is also available.
More stories
HSIC technology delivers low power consumption
Evatronix has announced the introduction of a High-Speed Inter-Chip (HSIC) compatible PHY IP for power and area savings in USB 2.0 chip-to-chip connections.
Web application demonstrates IP core capabilities
Evatronix has introduced an online application that demonstrates the capabilities of the company's JPEG 2000 Encoder IP core for SoC designers.
IP core is targeted for low-power applications
Evatronix's C65C02 65C02 compatible microprocessor IP core complies with the original 6502 Instruction Set Architecture by MOS Technology and is targeted for low-power applications.
I2S-SC controller introduces TDM mechanism
Evatronix has introduced the I2S-SC controller IP, which is compatible with the Philips I2S specification and all its modes.
IP core implements wide set of peripherals
Evatronix has released the 80186EC IP core - a 16-bit microprocessor compatible with the 80c186ec chip from Intel and can address a variety of possible applications.


