Controller enables DigRF implementation into ICs

By complementing its current silicon-proven Designware MIPI 3G DigRF Controller and PHY IP, Synopsys completes its IP portfolio for the MIPI DigRF v3 and v4 standards.

In addition, Synopsys is developing the Designware M-PHY(SM) - the physical layer for the MIPI DigRF v4 interface - in parallel with the ratification of the specification.

A single-vendor solution enables designers to lower the risk and cost of integrating the DigRF interfaces into baseband ICs (BBICs) and application processors, while speeding time to market of advanced LTE and Mobile WiMAX system-on-chips (SoCs).

MIPI Alliance's DigRF v4 is the latest generation of the standard that defines the interface between RF transceiver ICs (RFIC) and BBICs and addresses the increased data-throughput requirements for mobile terminals targeting 4G standard air interfaces such as LTE and mWiMAX.

The DigRF v4 specification also supports existing 3GPP standards such as 2.5G and 3.5G.

The low-power, area-efficient Designware 4G DigRF Master Controller implements the features defined for the protocol and PHY adaptation layers of the DigRF v4 rev 1.00 specification.

It has also verified interoperability with RFIC devices currently available on the market.

Configurability of the IP RTL provides flexibility for system-specific implementations, such as number of lanes, sublinks and diversity, while protocol-specific attributes including IQ sample size, frame scheduling and handling of timing-critical signals are software programmable.