Altera RapidIO passes Riolab testing
Altera
Altera RapidIO Megacore function version 9.0
Altera Corporation has announced that its RapidIO Megacore function, version 9.0, successfully passed Riolab's Device Interoperability Level-3 (DIL-3) testing.
Altera's Serial RapidIO IP is interoperable with components, systems and software using RapidIO technology.
The IP core works with Altera's Cyclone, Arria and Stratix FPGAs and Hardcopy ASICs.
Altera's Serial RapidIO Megacore function is designed to the RapidIO interconnect specification version 1.3.
The core supports x1 and x4 lane widths at 1.25, 2.5 and 3.125Gbps lane rates, and allows for physical-, transport- and logical-layer separation.
The endpoint IP core comes with test benches that provide interoperability with digital signal processor and switch vendors.
Altera offers a complete system-level, integration-ready Serial RapidIO solution that includes a Serial RapidIO IP core, reference designs and hardware-development platforms.
Designers can create custom systems to support their RapidIO architectures, including processor endpoints, digital-signal processor endpoints with signal processing megafunctions, RapidIO switches, and RapidIO bridges, including PCI, PCI-X, Hypertransport, system memory, and peripheral devices.
The Serial RapidIO Megacore function is available for download as part of the combined Quartus II Software/Altera MegaCore release on Altera's website.
The IP core is available as encrypted IP or as source code.
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