TSMC releases MS/RF RDK for foundry industry

Launched at TSMC's North American Technology Symposium in San Jose, the RDK initially targets 65nm process technology and aims to accelerate analogue, MS and RF designs and RF system-on-chip (SoC) verification and integration.

The MS/RF RDK is the result of a multi-year collaboration between TSMC and Cadence Design Systems and represents one of the initial deliverables of the TSMC Open Innovation Platform.

The RDK is intended to help resolve the challenge of full-chip verification of SoCs with analogue, MS and digital content.

It enables a top-down MS/RF design methodology and a system-level simulation flow to reduce design cycle time and encourage IP reuse.

The reference design in the RDK is an advanced Fractional-N phase-locked loop (PLL) developed in TSMC 65nm RF process technology and fully validated in silicon with accurate correlation between simulation results and silicon measurements.

The RDK includes a video tutorial and a step-by-step design manual.

It also comprises the complete PLL reference design database with schematics, layouts and simulation test benches, as well as a design flow and methodology introduction, silicon test reports, release notes specifying design tool and version requirements and a TSMC 65nm process design kit (PDK).

ST Juang, senior director of design infrastructure marketing at TSMC, said: 'The TSMC MS/RF RDK delivers a new level of confidence to our customers that complex MS/RF blocks can be created and accurately verified in the context of full-chip RF SoCs and taped out with high quality, thus ensuring first-pass silicon success.

'We continue to collaborate with our ecosystem partners to enhance the features and capabilities of the RDK to address emerging MS/RF design challenges.' The TSMC 65nm MS/RF RDK is available now in limited release and at no charge to selective customers during the second quarter of 2009.

General release to other customers is targeted for the third quarter of 2009.