Synopsys silicon-verifies DDR3 IP at 1,600Mbps

Using test chips manufactured in 65nm technology, Synopsys verified the operation of its DDR3/2 PHY and digital controller IP with DDR3 memory components and dual inline memory modules (DIMMs).

This gives designers confidence that the Designware DDR3/2 IP operates reliably at 1,600Mbps in a complete memory sub-system environment, taking into consideration the chip package, printed circuit board and associated DRAMs.

The Designware DDR3/2 IP is targeted at a broad range of high-performance applications such as digital home, digital office, data centre and storage, requiring bandwidth in excess of 1,066Mbps per pin, and provides backwards compatibility for DDR2-667 to DDR2-1066 devices.

To support the full range of DDR3 data rates, the Designware DDR3/2 IP includes built-in data training circuits to enable in-system calibration, offering more robust operation for the overall system.

As part of the data training sequence, the DDR3/2 IP includes the ability to remove bit-to-bit timing skew, which can occur on the chip, in the package or on the circuit board, to improve memory system timing budgets.

The Designware DDR3/2 PHY characterisation reports are available, providing a detailed analysis of all aspects of the DDR PHY to SDRAM interface, including clock timing specifications, write-and-read data eyes and a comparison of circuit simulation with silicon measurement.