Software supports Multi-Chip Modules and 3D chips

Multi-Chip Modules (MCM) and 3D chips are now supported, allowing testbench generation for VHDL, Verilog and STIL output formats.

Users now have the opportunity to verify more complex designs with several Boundary Scan components or dies, including interconnections by a comprehensive behaviour simulation.

'The fully automatic generation of testbenches guarantees a deeper validation and higher design quality of the target as well as the full functionality of all Boundary Scan structures in practical usage,' said Daniel Wilkinson, director of verification with XMOS Semiconductor.

'The Tapchecker MCM option was made available as agreed in our design process,' he said.

'We verified our JTAG/Boundary Scan implementation before tape out and then exported patterns from the same tool for our production test programme,' Wilkinson added.

Tapchecker is based on a modular platform architecture with central database and individually licensable modules for data import and export, as well as automatic test vector generation.

The software can be utilised for automatic testbench generation to simulate BSDL files and to provide test vectors for IC testers.

It is available for various operating systems such as Solaris, Windows and Linux, supporting IEEE 1149.1 and IEEE 1149.6.