Real Intent unveils next-generation lint tool

Ascent Lint is the next-generation lint tool in the Ascent early functional verification range of products.

It performs syntax and semantic lint checks for complex system-on-chip designs.

Ascent Lint 1.2 now offers rules from Starc Policy, Verilog and Systemverilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs and rules based on Real Intent industry know-how.

These rules cover the following areas: legal but dubious modelling indicating probable errors; differences between simulation and synthesis semantics; naming and RTL-coding conventions; subset restrictions to enforce modelling clarity and to reduce complexity; opportunities to improve simulation performance; operations with hidden or expensive implementation costs; downstream tool flow issues; network and connectivity checks for clocks, resets and tri-state-driven signals; module partitioning rules; and testability.

Ascent Lint features a fast engine and a low-noise report and is said to be simple to use for debugging.