Real Intent releases Meridian FPGA to verify CDCs

Meridian FPGA works with Altera's Quartus II software version 8.1 to verify clock domain crossings (CDCs).

It is an alternative to the ASIC design software.

Meridian FPGA offers four times faster CDC closure through automatic, template-free and powerful clock intent verification.

It verifies FIFO and protocol-driven CDC interfaces for maximal confidence.

Effects specific to FPGA platforms are automatically integrated in the verification process.

Meridian FPGA is integrated with Quartus II software to deliver verification confidence in a seamless flow.

Prakash Narain, chief executive officer of Real Intent, said: 'Reliable CDC verification is a growing problem for FPGA designers.' FPGA performs automatic clock intent verification by automatically extracting and verifying clock, reset, data and control crossings in the design to ensure reliable CDC operations.

Meridian FPGA supports Tcl and synopsys design constraint (SDC) interfaces and offers flexible debug and sign-off capabilities for easy CDC verification.