Lattice PAC software supports power manager

The PAC-Designer 5.2 software now supports two higher performance Power Manager II products: the ispPAC-POWR1014-2 and ispPAC-POWR1014A-2 devices.

The POWR1014/A-2 devices are suitable for integrating Hot Swap control, voltage rail supervision and power-supply sequencing ICs.

PAC-Designer 5.2 software also supports an expanded input operating frequency range of 40-400MHz for ispClock5400D devices and a graphical editor for phase and time-skew programming.

Lattice Power Manager II devices integrate programmable analogue and PLD technologies to support digital power-management solutions.

As more digital management functions are integrated, the verification step in the design flow depends on robust simulation technology.

The PAC-Designer 5.2 software provides a VHDL or Verilog HDL export feature to extract simulation models of the embedded PLD block featured on all Lattice Power Manager II devices.

This allows for functional verification of sequence and supervisory logic by the Aldec Active-HDL Lattice Web Edition simulator.

By adding HDL export features to PAC-Designer software, power supply sequencing, reset signal distribution and other digital logic integrated into a Power Manager II device can be modelled with IEEE Verilog HDL or VHDL.