IC Compiler enables faster design for video market

It delivers up to 2.5 times faster performance on multicorner/multimode (MCMM) designs and enhanced In-Design technology IC Compiler's In-Design technology helps prevent late-stage surprises by enabling signoff-accurate static timing analysis, rail analysis and physical verification during design.

The software release has production support for all known 28/32nm design rules for major foundries, with several customer tapeouts underway.

IC Compiler provides faster time to initial floorplan creation and on-demand loading, which offers two to three times faster time to final floorplan creation.

IC Compiler 2010.03 also includes two times faster pre-route feasibility engines and generates interactive reports that help reduce iterative cycles during early stages of design.

Faster MCMM scenario processing, core engine improvements and multimode clock tree synthesis deliver faster timing convergence.

IC Compiler's In-Design technology reduces design iterations by enabling signoff accurate analysis and physical verification during design.

In-Design enhancements in the 2010.03 release include dynamic rail analysis with Primerail and DRC auto fixing with IC Validator.

The 2010.03 release introduces a new leakage optimisation engine capable of handling more than 20 leakage variants.

This is achieved by using In-Design technology with Primetime to deliver considerable leakage reduction while preserving signoff timing.

This capability, combined with advances in post-route leakage optimisation and MCMM leakage scenario optimisation, enables IC Compiler 2010.03 to deliver double the leakage savings in half the time.