IAR Systems launches Visualstate 6.20

IAR said that the latest release of Visualstate provides improved speed and memory efficiency, enabling rapid verification of more complex designs.

This makes IAR Visualstate even more suitable as a tool for small embedded designs that require high integrity.

IAR Visualstate is a set of development tools for designing, testing and implementing embedded applications based on state chart diagrams.

It provides advanced verification and validation utilities, and generates compact C/C++ code that is 100 per cent consistent with the system design.

In addition, its tight integration with IAR Embedded Workbench enables true state machine debugging on hardware, with direct graphical feedback at various levels of detail.

Designs generated by IAR Visualstate can already be found in applications such as blood glucose meters, underwater breathing apparatus, coffee machines and office ventilation control.

There are virtually no restrictions on the type of modelling constructions that can be used for verification, and the tool includes a comprehensive set of optimisations that reduce runtime and memory requirements.

This latest release also features improved compliance to MISRA C:2004.

The generated code in the readable code format has been closely aligned with the MISRA C:2004 guidelines and with the guidelines published by MIRA on MISRA C:2004 in the context of automatic code generation.

IAR Visualstate 6.20 also has the ability to exclude specified design regions from code generation: it is possible to mark state machine regions and individual states on any hierarchical level for exclusion from further processing.

The developer then has the option to confirm during code generation, verification and validation whether the marked regions should be excluded or included.

This feature can be used to create simple product differentiation, or to generate different debug scenarios for code generation, validation and verification.

An example code index gives short descriptions relating to each of the accompanying code and applications examples.

By designing a system of state machines in IAR Visualstate, the developer is able to use the formal verification feature to uncover issues or anomalies in a design that would be virtually impossible to cover in full by writing test suites.