Forte launches synthesis software for design teams

The company claims that its flagship Cynthesizer SystemC synthesis software, which is used in production application-specific integrated-circuit (ASIC) and system-on-chip (SoC) silicon tape-outs, includes new capabilities that reduce design time, improve power utilisation and accelerate verification performance.

Both products, available now in volume shipments, simplify hardware and electronic system level (ESL) design to improve circuit performance and reduce chip costs.

According to Brett Cline, Forte's vice-president of marketing and sales, the Cynthesizer product range raises the abstraction level of design by automating mundane tasks while providing the quality of results, power reduction and support for the overall ESL design flow required for hardware design.

The company's Cellmath technology and patented intellectual property (IP) improves the quality of results by creating better data-path components.

Integrating Cynthesizer with Cellmath Designer data-path optimisation and Cellmath IP enables design teams to create better designs using more optimised building blocks.

Cynthesizer Ultra uses Cellmath Designer as an embedded data-path optimisation capability to create data-path components as needed for use in the high-level synthesis process.

These products work together to perform automated design-space exploration that will search for the best set of components for each individual design.

With these techniques, Cynthesizer Ultra improves power consumption and timing and reduces area by up to 40 per cent compared with previous versions.

Cynthesizer Ultra adds access to the Cellmath IP library, including the advanced, floating-point functional units used by graphics companies.

This IP can be accessed directly from the SystemC through an automated flow.

Cynthesizer includes a new schedule analysis detail view, which allows designers to converge on their final design more quickly by giving them specific direction to correct or improve areas of the design that may not meet their quality-of-results goals.

High-level synthesis automatically builds the design 'schedule', which includes the creation of the data path and finite state machine (FSM) to meet a given set of user-directed and/or hardware design constraints.

When these constraints cannot be met, Cynthesizer gives the user specific direction for further input, reducing the required design time.

Cycle Accurate simulation technology is claimed to improve verification performance.

Using Cynthesizer's automated methodology management software, designers can quickly execute behavioural simulations and high-level synthesis and utilise Cynthesizer Cycle Accurate simulation to accelerate the output register transfer level (RTL) implementations.

With speeds up to 20 times faster than traditional RTL simulation, designers have a cost-effective and integrated solution to meet their verification challenges, according to the company.

Cynthesizer also includes updates to its Cynware IP interface library.

Forte claims that designers can use its pre-verified library and faster memory interface support for greater flexibility, better performance and lower power.

Additional features and optimisations further reduce circuit power utilisation and improve tool runtime and capacity.

The company will demonstrate Cynthesizer, Cynthesizer Ultra and its Cellmath range of products in Booth 750 at the 47th Design Automation Conference (DAC) on 14-16 June at the Anaheim Convention Center in Anaheim, California.

Cynthesizer comes standard with Forte's transaction level modelling (TLM) synthesis capability, complete memory generation subsystem, fixed-point support and streaming interface IP.

Cynthesizer Ultra adds the Cellmath data-path optimiser and floating-point support.

Pricing starts at USD275,000 (GBP192,000).

Cynthesizer's Partitioning and Interface Generator features start at USD40,000 as an add-on to Cynthesizer.