Encounter digital implementation system launched
Cadence Design Systems
Encounter digital implementation system
Cadence Design Systems has launched the Encounter digital implementation system, a configurable platform delivering scalability and support for parallel processing across the design flow.
The system also brings efficient new core memory architecture, delivering higher-performance, higher-capacity design closure for single CPU operations.
Along with enhanced performance and capacity, the Encounter digital implementation system offers new technologies for silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimisation in early stages of the design flow.
In addition, multiple enhanced implementation and design closure technologies are being introduced, including automated floorplan synthesis, end-to-end multi-mode multi-corner optimisation, variation-tolerant and low-power clock tree and clock mesh synthesis, high-capacity placement and optimisation, 32-nanometer routing and manufacturing-aware optimisation, signoff-driven implementation, and flip chip design features.
More stories
Cadence integration platform enables SoC design
The Cadence Open Integration Platform enables design teams to deliver higher quality, optimised SoCs with lower realisation costs.
Cadence improves Virtuoso IC design platform
Cadence Design Systems has announced performance, capacity and usability enhancements to its Virtuoso IC design platform.
Cadence printed circuit board has new features
Cadence Design Systems has released its Cadence Allegro and OrCAD printed circuit board (PCB) software with a range of new features.
Cadence unveils Incisive Enterprise Verifier
Cadence Design Systems has introduced the Incisive Enterprise Verifier (IEV), an integrated verification solution delivering the dual power of formal analysis and simulation engines.
Cadence unveils Virtuoso circuit simulator
Cadence Design Systems has announced the availability of the Virtuoso Accelerated Parallel Simulator (APS), its next-generation circuit simulator.
