Edxact highlights debugging tools at DAC 2010
Edxact
Debugging tools
Post-layout verification specialist Edxact is to showcase the latest enhancements of its parasitics reduction and analysis tools at the European EDAVillage at DAC 2010.
Among the highlights of the tool releases of 5.0 of Jivaro and 3.2 of Comanche are hierarchical file handling, additional features to drive the selectivity options and integrations into different graphical user interfaces in order to facilitate interactive network debugging facilities.
The Jivaro v5.0 netlist reduction tool features the ability to group parasitics by property in order to remodel them selectively.
The feature is useful for all downstream tools requiring preservation of structure and details on interconnections.
Current customers used this feature for the analysis of voltage drop, electromigration, electrostatic discharge and other simulations.
V5.0 also features enhancements on Edxact's Pathfinder algorithm, an important selectivity feature to accelerate simulation time.
Jivaro is a netlist reduction software platform that enables designers to remodel back-annotated design data in a way that enables them to speed up post-layout simulations suffering from an accrued amount of parasitics.
The software is compatible with all extraction and simulation tools.
Comanche, a parasitics analysis tool, can interactively debug parasitics-related problems based on a graphical layout view in Cadence's Virtuoso design environment, or in Springsoft's Laker design environment.
Comanche 3.2 benefits from a new toolbox that generates helpful statistics on a net-per-net basis and allows the user to compare two different extracted netlists.
Commanche, dedicated to problems related to interconnect, has been boosted by an order of magnitude for very large nets.
The tool reads netlists in standard formats (DSPF, SPEF) and analyses parasitic networks quickly and accurately.
A typical application of Comanche is the determination of the compliance with ESD design rules.
Comanche can be run in batch mode for large post-layout verification runs.
It can also be used in interactive mode.
For interactive mode, tight integrations into major design environments have been developed.
More stories
Mediatek selects Jivaro netlist reduction platform
Edxact and Mediatak have entered into a strategic relationship to deploy Edxact's netlist reduction platform for analogue circuits.
Visionpro from Cognex enables laser marking specialist to ensure component traceability weblink
Asys Automatisierungssysteme, a laser marking specialist based in Dornstadt, Germany, has incorporated Cognex’s Visionpro vision software into its Insignum 2000 laser marking system to ensure complete component traceability.
Rittal software provides support for planning and verification of low-voltage switchgear weblink
Version 6.0 of Rittal’s Power Engineering software is designed to provide support for the planning and verification of standardised Ri4power switchgear, as well as low-voltage switchgear consisting of the TS 8 enclosure system and the Riline60 modular busbar system.
B and R works with Eplan to create seamless interface between development tools weblink
B and R and Eplan have developed a seamless interface between the B and R Automation Studio and Eplan Electric P8 development tools, which are suitable for mechanical, electrical and software engineering.
Rittal offers calculation software for choosing efficient enclosure climate control weblink
Rittal’s Rittal Therm calculation programme enables users to find the most efficient means of climate control for their enclosures.




