EDA upgrades Tanner Tools Pro and Hiper Silicon

This includes an interactive autorouter, the SDL Router and a layout device generator called Devgen.

Both these additions increase designers' productivity and speed up development of full custom analogue IC and MEMS design.

The products will be demonstrated at the Design Automation Conference in San Francisco on 27-30 July 2009 at Booth 3655.

SDL Router is an automatic routing engine integrated directly into Tanner EDA's schematic driven layout (SDL) software.

It speeds layout by automatically routing non-critical nets while allowing the designer to focus on routes that require expensive hand craftsmanship for performance or addressing analogue-sensitive nets or parts of nets.

The router is interactively controlled by a layout engineer.

It natively uses the routing geometry created by the user and runs on all or a specified subset of nodes on each pass.

Users can manually route part of a net and have the router automatically finish routing the net.

As a result of the router's integration with Tanner EDA's SDL software, users can highlight and rip up nodes, manage the manual and automatic routing status and implement engineering change orders (ECOs).

Devgen allows analogue layout designers to become more productive by automating much of the task of laying out the devices.

It provides parameterised layout generators that are configured for any process to help ensure error-free layout.

By using the Devgen wizard and answering a few questions about the layers involved and the design rule checks (DRCs), designers can create parameterised cells of common devices without having to write code.

Devgen includes layout generators for capacitors, resistors, inductors, Mosfets and diodes.

SDL Router and Devgen are claimed to increase the speed and quality of custom layout and to encourage good design practices by keeping close synchronisation between the schematic and the layout.

SDL improves productivity by automating the instancing of cells and parameterised devices and placement quality by displaying real-time node flylines.

It also helps avoid routing congestion and tracks an engineer's progress to help manage workflow.

Version 14.10 of Tanner Tools Pro and Hiper Silicon also includes improved Verilog-A integration to reduce analogue simulation runtimes when simulations include digital blocks.

Hiper Verify runs Calibre and Dracula foundry files natively, without conversion or modification, as well as running Assura foundry files natively.

Safe-operating-area (SOA) checks in T-Spice have been added, so models stay valid and circuits operate correctly.

The software's interactive DRC displays violations in real time during layout editing that help layout engineers to create compact, error-free layouts the first time.

Spacing distance is displayed in real time while the layout is edited and can prevent editing from getting closer than the minimum distance.