EASIC suite enables Nextreme design implementation

The eTools 8.1 tool suite delivers a robust ASIC-grade design flow.

New features and enhancements in eTools 8.1 enable designers to reduce overall design time by up to 40 per cent, while increasing design performance by up to 30 per cent compared to the previous eTools 8.0 suite.

New features and utilities within eTools 8.1 focus on reducing design conversion and implementation time, while enhancing the overall quality of results.

The tool suite now includes a complete floorplanner with interactive regioning capability and a detailed placer based on a set of new advanced proprietary algorithms that are optimised for EASIC's single via customisation logic architecture.

Both utilities also combine to facilitate rapid timing closure on complex new ASIC designs.

eTools 8.1 also includes capabilities that enable rapid RTL design conversion from traditional design platforms such as FPGA and ASIC.

The design flow enables designers to focus their efforts on achieving the desired functionality and timing of their design.

As a result, designers are able to rapidly progress from their initial RTL to a netlist-level or placed-gates handoff to EASIC.

Designers have the option of performing synthesis using industry-standard logic-synthesis tools.