Azuro Powercentric tool included in TSMC's ISF
Azuro
Powercentric low-power clock tree synthesis tool
Azuro has announced the inclusion of its Powercentric low-power clock tree synthesis tool in the second phase of TSMC's Integrated Sign-off Flow (ISF) in 65nm.
The ISF is an automated RTL to GDSII chip implementation flow that integrates TSMC foundry technology files, pre-qualified library, IP, EDA tools, and sign-off margin recommendations into a fully automated scripted production-quality flow.
With the second release of the ISF, TSMC customers are able to tapeout with Powercentric using either a Cadence or Synopsys-based PandR flow and reduce clock power by 25 per cent or more.
Azuro and TSMC worked closely together during the development and beta testing of a Cadence PandR-based ISF to ensure that the insertion of Powercentric into this flow was also completely transparent to its users.
Using the ISF, chip design teams taping out to TSMC's foundries can now exploit Powercentric to reduce clock power within an extensively pre-tested pre-integrated production-ready flow including a full set of automated scripts and user documentation for either the Cadence or Synopsys PandR tools.
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