Atrenta launches design closure seminar series

These seminars will assist chip companies to build better products, both faster and more economically, by detecting and mitigating design risks earlier in the design process.

Atrenta will visit major semiconductor hubs around the world to share the latest technologies and methodologies for early design closure.

The Design Closure Stimulus Package seminar series will run during 2009 and 2010.

Presented by the company's technology experts, these seminars will be aimed primarily at engineering managers, chip architects, RTL designers, design methodology engineers and IP design/verification engineers seeking to implement correct designs rapidly through the integrated use of a variety of design automation systems.

The free seminars, typically scheduled for 90 to 120 minutes during lunch, will cover a variety of topics, including clock domain crossing verification, design for test, constraints analysis, power management, modelling of physical effects at RTL and platform-based design techniques.

Detailed case studies will demonstrate how to improve methodologies and achieve better early design closure.

Pre-registration is required for these events.

Currently scheduled seminars are as follows: Catching CDC and DFT Bugs, 29 January in Noida, India, 2 February in Bangalore, India; Eliminate Power Bugs and Hogs, 5 February in Santa Clara, California, US.