USB 2.0 device features ADWG capabilities

It enables the stimulation and analysis of digital interfaces, streaming data to/from a PC to 16 data lines at up to 10MHz, with six additional control lines for repetitive sequence generation, in/out clocking or trigger definition.

With its 8MByte embedded memory buffer and 100MHz operation on all 16 digital lines, GP-24100 is said to be a powerful and versatile general-purpose PC-based test tool that ideally complements conventional laboratory equipment for digital electronic system design, test and debug.

The GP-24100 is said to make generating and collecting digital data to stimulate and analyse electronic system easy, with the maximum sustained throughput via USB of up to 30Mbyte/s.

The supplied 8PI Control Panel Software offers graphical scripting (TCL/tk) and programming (C/C++) interfaces to automate tasks and bridge between programming environments and hardware prototypes.

The 8PI software allows the user to define I/O clocks, repetitive sequences, and trigger patterns; and to automate tasks or build custom applications users can use the TCL scripting environment or C, C++ DLLs.

It can also set repetitive and cumbersome laboratory tasks, such as controlling a digital-to-analogue (DAC) converter, sending a stimulus to a custom IP block in an FPGA, or to create an arbitrary stimulus and collect results.

With its ADWG/Pattern Generator mode of operation, GP-24100 allows the user to generate extended depths of arbitrary digital stimuli, directly from a PC through a USB connection - and create 16-bit wide arbitrary patterns at up to 100MHz using the 8MB internal memory buffer.

GP-24100's analyser mode of operation transforms the compact test box into a simple logic analyser to collect and analyse digital data, sampling 16-bits at up to 100MHz and storing data in 8Mbytes of internal memory.

There are many ways of interacting with GP- 24100: Windows GUI, C/C++ and TCL/tk.

This developer tool is suited to a range of applications, including: JTAG (IEEE 1149.1) access; logic/state analysis/data logging; ADWG/pattern-generator; serial protocol access; FPGA/CPLD serial or parallel configuration; parallel protocol access (up to six control lines/16 data lines); bus-master emulation; SRAM; flash interface; system debug and system prototype access; bidirectional protocol analyser; IP prototyping and evaluation; recorder/player tools; ADC/DAC test and control; pattern waveform generation, and so on.

Optional extras include SPI and IC bus exerciser/analyser modes of operation.