Casio WLP technology added to dummy component line
Practical Components
Casio Micronics WLP wafer chip size package
Practical Components has extended its line of dummy components with the addition of the Casio Micronics WLP wafer chip size package, which is suitable for installation in surface-mount technology.
WLP is a new technology for semiconductor devices that enables rerouting of the copper traces and encapsulation of the chips in epoxy resin while the wafer is intact.
It can be differentiated from other IC packages by its production method - all the WLP packaging processes are carried out on a single silicon wafer.
Aluminium pads are interconnected by Cu redistribution wirings to Cu posts.
Epoxy resin is filled to protect the structure.
Solder bumps (both eutectic and lead-free) are applied on the Cu posts.
WLP is suitable for applications such as mobile phones and digital cameras.
In addition, W-CSP has been adopted for new classes of devices such as power Mosfets to enable their use in miniaturised equipment.
Benefits of WLP include: reduced form factor (small footprint: 1/4 compared with QFP, reduced package height: less than 0.65mm/LGA, less than 0.80mm/BGA; conventional SMT chip bonders can be used for mounting W-CSPs on the PCB; cost benefit can be obtained if high yield and small-size ICs are processed because the process cost is wafer-dependent.
'The Practical Components WLP dummy component will help users to learn and assemble with this new product,' said Kevin Laphen, president at Practical Components.
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