Achronix demonstrates DDR3 reference design

The SPC60, a compact development kit for the Speedster range of 1.5GHz FPGAs, demonstrates 1066Mbps DDR3 reference design available for out-of-the-box integration with customer designs; eliminating difficult memory interface implementation and verification challenges.

The SPD60 FPGA has four embedded DDR3 controllers.

A full-speed (533MHz, 1066Mbps), full-width (72 bit) DDR3 interface can be built using no programmable logic resources.

It comes complete with reference design RTL code and documentation, which can be modified as required.

Neither the controller nor the reference design requires a licence fee.

The development board is designed for systems engineers who need access to both high-end 10.3Gbps SerDes and DDR3 memory in a compact platform.

SPC60 is suitable for applications where there is a growing need for high-performance (both logic and interconnect), such as in the high-end networking, signal processing, and high-performance computing markets.

With the SPC60 development board, designers can exercise the full performance of the Speedster device, run prepared designs provided with the kit, configure the device with a new design, and debug that design on a common platform.

Achronix-specific and industry-standard development tools are provided, along with a collection of standard reference designs.