Inphi releases 28G BER receiver reference design
Inphi
28G BER receiver
Inphi Corporation has introduced a 28G bit error ratio (BER) receiver reference design.
The 28G BER receiver is for research and development or production testing of emerging high-speed protocols from 13 to 28Gbps, including 100 Gigabit Ethernet, 40G differential quadrature phase shift keying (DQPSK), 14G Fibre Channel, and 100G dual-polarisation quadrature phase shift keying (DP-QPSK).
The reference design is claimed to help accelerate time-to-market for test and measurement vendors designing 28G test platforms.
For high-speed data links, BER testing is the most fundamental test at the physical layer, as it measures whether the data bits are correctly transmitted across the link.
The Inphi 28G BER receiver reference design addresses the challenge of designing a high-speed front-end at 28Gbps, and integrates an Inphi chipset in a high-performance design.
The reference design, together with a 12.5G BERT and a 28G high-speed test pattern generator, comprise a complete 28Gbps test solution.
For test applications requiring clock recovery, the 28G BER receiver reference design provides a buffered copy of the high-speed input data stream, which can be supplied to an optional clock recovery unit to generate a recovered clock.
The 28G BER receiver reference design is based on an Inphi chipset of a 5081DX 50Gbps 1:4 demultiplexer, 25717CF 25Gbps 1:2 fanout, and 20709SE 20Gbps 2:1 selector.
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