Sumitomo uses Altera's 40nm Stratix IV GX FPGA
Altera
Stratix IV GX
Sumitomo Electric Industries is using Altera's 40nm Stratix IV GX FPGA in a low-density parity-check (LDPC) high-speed measurement system.
This verifies the forward error correction (FEC) code for high-speed digital signal processing (DSP).
Sumitomo's high-throughput LDPC system features a novel encoding and decoding algorithm capable of improving the signal quality in applications that require efficient data transmission, such as image processing, next-generation optical memory, high-definition (HD) digital video broadcasting, mobile broadband communications and optical networking.
Takashi Maehata, assistant general manager of the transmission-system department at Sumitomo Electric Industries, said: 'Altera's Stratix IV GX FPGA provides us with a cost-effective, single-chip solution that delivers best-in-class performance and data-rate speeds, allowing us to realise more than 100Gbps performance in our LDPC system.
'Obtaining this level of performance would not have been possible without Stratix IV GX FPGAs and their integrated 8.5Gbps transceivers.
'As a result of using Altera's Stratix IV GX FPGAs, our LDPC system achieves a throughput of 132Gbps encoding and 24.48Gbps decoding.' Altera Stratix IV GX FPGAs and Quartus II design software provide Sumitomo with a seamless development environment from algorithm to automatic HDL generation.
The Stratix IV GX FPGA-based LDPC system interfaces with a multi-Gbit analogue/digital converter (ADC) and features a Nios II embedded processor.
The embedded processor operates a TCP/IP protocol stack and facilitates the LDPC encoder and decoder.
The system's circuits were developed using the Quartus II software and the DSP Builder and SOPC Builder tools.
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