PCI Express-to-HSS bridge for the CAP12-120

This bridge design has been implemented in the award-winning LatticeECP2M FPGA.

The solution uses the LatticeECP2M's SERDES and a Lattice PCI Express Intellectual Property (IP) core.

Sean Riley, vice-president of high-density solutions at Lattice, said: 'The LatticeECP2M family provides a very cost-effective alternative to the high-end SERDES-based FPGAs and ASSPs that traditionally have been used for PCI Express applications.' The Lattice FPGA solution is used in the Intel CAP12-120 reference design, based on the Intel Celeron M 915GM processor and chipset.

To address the voice, video and data communications needs of small and medium businesses and enterprises (SMB/SMEs), Intel has added two versatile yet affordable multi-system business gateway reference designs to its family of converged solutions platforms.

The Intel CAP12-120, announced at Voicecon 2008, is a proof-of-concept design for software-based IP-PBX/MSBG solutions.

It enables developers to quickly and cheaply build a converged communications device for up to 120 seats.

These solutions deliver a variety of services and can be scaled and modified easily in software to meet the requirements of different customer premises.

The fully integrated platforms include all the necessary hardware and software components for building cost-effective IP-PBX/MSG solutions, reducing the time, effort and development cost of these platforms.

The LatticeECP2M family provides an ideal FPGA platform for implementation of high performance serial protocols such as PCI Express and Gbit Ethernet.

The Lattice PCI Express IP, combined with Lattice's own high-speed SERDES, and the economical, low power, high-performance LatticeECP2M fabric, gives designers a powerful platform for satisfying high-performance bridging and co-processing needs.

The flexibility of the LatticeECP2M fabric provides designers with a platform to develop a variety of applications while still meeting aggressive cost targets.