Lattice FPGA devices include SERDES channels

The solution utilises 17 Serialiser/Deserialiser (SERDES) channels in the LatticeSC/M devices, including the Lattice SFI5 soft IP core, and enables flexible and high-performance 40Gbps systems.

The LatticeSC/M FPGA devices include four to 32 channels of high-speed SERDES capable of supporting data rates from 600Mbps to 3.8Gbps.

The FlexiPCSO physical coding sublayer block embedded in the devices supports an array of popular communications data protocols, including SONET/SDH, Gigabit Ethernet, Fibre Channel, 10 Gigabit Ethernet (XAUI), PCI Express and Serial RapidIO.

The LatticeSCM FPGA range also includes pre-engineered embedded IP cores (SPI4.2, 1G/10G Ethernet MACs, PCI Express, memory controllers and CDR) implemented in Lattice's low-power MACO (masked array for cost optimisation) structured ASIC blocks.

The LatticeSCM range, as well as the LatticeSC range, which does not support MACO functionality but is otherwise identical, provides five logic density points between 15K and 115K LUTs; four to 32 channels of embedded SERDES; embedded memory capacity from 1MB to 7.8MB of dual-port block RAM; and general-purpose 2Gbps Purespeed I/O ranging from 139 to 942 I/Os.

Each device also features eight analogue PLLs, 12 digital DLLs and ample clock routing for optimum clock flexibility.

The LatticeSC/M FPGAs are supported by the ISPleverA version 7.2 software design tool suite.