Lattice enhances design tool software

The ISPlever 7.2 software now supports Lattice's 'clock boosting' flow for the LatticeECP2 and LatticeECP2M FPGA ranges.

Clock boosting can result in up to a five per cent increase in Fmax with no additional user input.

In addition to performance improvements, ISPlever Version 7.2 improves productivity with additional control, analysis and workflow enhancements.

It also includes the latest release of Synplify Pro, an advanced FPGA synthesis solution from Synopsys.

Using place and route techniques, ISPlever can now analyse a design and automatically choose the most appropriate algorithm for the design's topology.

For example, in a design with a connectivity pattern that is more likely to lead to routing congestion, the tool will automatically choose an algorithm that is appropriate to find better results in less time.

In some cases the chosen algorithm can reduce runtime as much as 30 per cent.

Properly constrained clock domains and cross-domain data paths are critical to closing timing in multi-clock designs.

The Trace static timing analysis report now includes a 'clock domain analysis' section.

This is useful for understanding the nature of the clock domains in the design, how they are currently constrained, where there are gaps in the constraint set and the data paths that exist between the clock domains.

In addition, the ISPlever 7.2 tool suite gives more user control over the use of Global Set/Reset routing.

This can result in improved routability and performance for designs with demanding routing requirements.

Also in this release, messages issued by the software's Project Navigator may be traced through a mouse click directly to the related line of source text opened in the user's editor.

Source files may be imported using a list file, which eases the sharing of files between design tools.