FPGA ideal for next-generation space systems

The FPGA is also said to be ideal for systems supporting interplanetary missions.

The off-the-shelf Xilinx Virtex 5QV FPGA is claimed to offer the industry's highest-density performance and integration capabilities for complex systems that would otherwise require rad-hard ASIC devices with their high development costs and long lead times, or traditional one-time programmable (OTP) solutions.

The combination of rad-hard and re-configurability enables a reduction in risk to critical programs by allowing minimal-cost, last-minute design changes and even redesigns after launch.

The FPGA is one of the ways Xilinx is addressing the programmable imperative that system developers face given the high-cost and risk of custom chip development and rigorous demands for higher-performance and integration.

The Virtex-5QV device joins the FPGAs, IP, ISE Design Suite development tools, kits and support that make up Xilinx's Targeted Design Platforms for delivering programmable solutions that help developers avoid the high cost of ASIC development and still meet the performance and integration requirements specific to their markets.

Xilinx claimed that the Virtex-5QV is the world's largest rad-hard reconfigurable logic device and is well suited to offer high performance in next-generation space systems and capability in applications such as video display, communications, radar, encryption, packet processing and control.

The radiation-hardened version of the commercial Xilinx Virtex-5 FPGA was developed under sponsorship by AFRL's Space Vehicles Directorate.

The rad-hard features in the Virtex-5QV devices are backed by high standards of in-beam testing by the Xilinx Radiation Test Consortium (XRTC) and equivalent to millions of device-years in space-radiation environments.

Xilinx said this means Virtex-5QV FPGAs provide exceptional protection against single-event upset (SEU), total immunity to single-event latch-up (SEL), high tolerance to total ionising dose (TID), as well as data-path protection from single-event transients (SET).

For example, the Virtex-5QV FPGA configuration memory provides nearly 1,000 times the SEU hardness of the standard cell latches in the commercial device, while configuration control logic and the JTAG controller have been hardened with embedded triple-module redundancy.

The devices are built on the second-generation ASMBL column-based architecture of the Virtex-5 family with support in Xlinix's ISE Design Suite.

Virtex-5QV devices integrate many of the same hard-IP system level blocks, such as flexible 36-Kbit/18-Kbit block RAM/Fifos, second-generation 25x18 DSP slices, power-optimised high-speed serial transceiver blocks for enhanced serial connectivity, and PCI Express compliant integrated Endpoint blocks.

The Virtex-5QV device offers 130,000 logic cells, 320 DSP Slices supporting fixed- and floating-point operations, and 836 user I/Os programmable to more than 30 different standards for applications and ease of interfacing to a variety of system components.

The Virtex-5QV family is also said to provide the industry's first integrated high-speed connectivity solution for space with 18 channels of 3Gbps multi-gigabit serial transceivers for chip-to-chip, board-to-board and box-to-box communication.