Actel announces RTAX-DSP prototype FPGAs
Actel
Actel RTAX-DSP prototype FPGAs
Actel has announced the availability of RTAX-DSP prototype FPGAs, enabling hardware demonstration and timing validation of designs targeted to Actel's RTAX-DSP space-flight FPGAs.
The devices have the same pin assignment, mechanical footprint and identical timing properties across the full military temperature range (-55 to 125C) as their space-qualified counterparts.
Providing a flexible alternative to expensive radiation-hardened ASICs, RTAX-DSP FPGAs feature up to 120 multiply-accumulate DSP mathblocks, protected against radiation-induced single-event upsets (SEU) and single-event transients (SET).
The RTAX-DSP FPGAs use the same 0.15um UMC wafer-fabrication process and the same antifuse programmable interconnect technology that are used in the RTAX-S FPGA family.
RTAX-DSP FPGAs offer high performance at densities of up to four million equivalent system gates and 840 user I/Os for space-based applications.
The embedded DSP mathblocks feature 18 x 18-bit multiply-accumulate blocks enabling efficient implementation of DSP building blocks, such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast Fourier transforms (FFT).
Each mathblock is capable of operating at 125MHz across the full military temperature range.
The RTAX-DSP family of FPGAs is fully supported by the Actel Libero Integrated Design Environment (IDE).
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