Achronix uses Signali cores for Speedster 1.5GHz

These are high-performance 128-bit key-size AES cores from Signali.

They are targeted at 10, 40 and 100Gbps applications.

They demonstrate the speed of the Speedster FGPA fabric, as well as the balance between throughput performance and resource minimisation achieved by the Signali cores.

Ali Burney, Serdes and IP marketing manager for Achronix Semiconductor, said: 'High-end 10/40/100G applications demand the highest-capability encryption engines to ensure security.' The Achronix Speedster range, brought out in September 2008 and offering three-times the performance of conventional FPGAs, targets traditional ASIC applications requiring high data-throughput.

Many of these also require sophisticated encryption algorithms to thwart hacking attempts.

To achieve the performance and resource-utilisation targets, Signali implemented two configurations for the AES IP cores: a 16-bit core, aimed at 10Gbps applications and featuring a pin-efficient 16-bit data path, while a second, 128-bit data path core targets 40 to 100Gbps applications.

Both cores use 128-bit keys and operate in CTR (counter) mode, designed for use in high-performance applications such as GPON (gigabit-capable passive optical network).

The cores are provided in standard Verilog or VHDL RTL, together with simulation models, test benches and complete documentation.

Signali uses its Quattro technology to transform high-level descriptions of data-intensive functions, such as AES, automatically into high-performance RTL.

These tools allow rapid algorithm and micro-architecture exploration at the design level, allowing the Signali's designers to quickly choose the best solution for specific implementation platforms.

Quattro enabled Signali's engineers to maximise usage of the capabilities of the Achronix Speedster FPGA architecture.