Silicon Labs releases clock multiplier IC

The Si5315 meets or exceeds the performance, integration, frequency and jitter requirements of the 1G and 10G Synchronous Ethernet (SyncE) market.

It supports 10G line encoding rates (161.13MHz) in addition to Sonet/SDH and Ethernet frequencies.

The device requires no external phase-locked loop (PLL) components, simplifying line card design and frequency translation in carrier Ethernet switch routers (CESRs), wireless backhaul, 3G/4G base stations, multi-service access platforms, passive optical networking, IP DSLAM and T1/E1 infrastructure.

As service providers upgrade legacy circuit switched networks to more cost-effective carrier Ethernet/IP networks, communications equipment suppliers face challenges when translating between legacy Sonet/SDH and Ethernet clock frequencies.

Existing SyncE clock ICs and voltage-controlled crystal oscillator-based module level systems are limited by a combination of poor jitter performance, limited frequency flexibility and lack of integration, which ultimately make these traditional systems difficult to use.

The Si5315 provides the lowest jitter of any SyncE clock IC in the industry, at less than 0.6 ps rms phase jitter, meeting the jitter requirements specified by ITU-T G.8262 and providing significant margin to Gigabit Ethernet (GbE) and 10 GbE PHY jitter requirements.

It achieves this level of performance by using Silicon Labs' DSPLL technology to integrate all key components of a high-performance analogue PLL on chip, thereby providing high immunity to system noise sources.

For ease of use, the Si5315 generates more than 200 of the most popular frequency translations required in SyncE line card applications, simplifying design and reducing BOM cost and complexity.