IPs targeted at handset communication systems

The 55nm 12-bit 80MSPS IQ analogue-to-digital converter (ADC) and IQ digital-to-analogue converter (DAC) IPs reach a maximum sampling frequency of 80MHz and deliver 12-bit resolution capability.

The IQ ADC adopts the pipelined architecture, fit for a range of high-resolution applications, and a single-clock input to control all internal conversion cycles.

It also comes with digital calibration function for digital error corrections.

The IQ DAC is a current-steering type with segmented architecture of seven thermo codes plus five binary codes.

It is designed to minimise the glitch energy and DNL, and provides high dynamic performance.

'Consisting of AFE or MIMO AFE with an auxiliary-ADC, an auxiliary-DAC and a PLL, our solution is a great fit for communication applications,' said YK Tseng, associate vice president at Faraday.

'Besides, to minimise the system-BOM cost, we adopt approaches such as size-optimised LDO as part of the AFE sub-system, use reference circuits that do not require off-chip capacitors and design the ADC input interface directly onto RF chips,' he added.

The 12-bit 80MSPS IQ ADC/DAC is available at UMC 55nm logic SP/RVT Low-K process.

Faraday also provides a complete design kit, which includes datasheet, application note, silicon validation report, physical design database, behavioural model, LVS netlist, timing model and evaluation board.