ADI launches six- and 12-channel clock buffers

ADI claimed that its 12-channel ADCLK954 LVPECL and ADCLK854 LVDS/CMOS and six-channel ADCLK946 LVPECL and ADCLK846 LVDS clock fan-out buffers provide up to four times as many clock channels on a single chip, with better combined jitter and skew performances than competing devices.

Jitter is as low as 75fs (femtoseconds) for ADI's LVPECL (low-voltage positive-emitter coupled logic) fan-out buffers and 100fs for its LVDS (low-voltage differential signalling)/CMOS fan-out buffers.

In addition, the ADCLK9xx clock buffers offer a low 9ps (picosecond) skew.

The ADCLK854 clock buffer also offers 24 CMOS (complementary metal oxide semiconductor) channels.

With these specifications, the clock buffers are effective for clocking high-speed ADCs (analogue-to-digital converters) and DACs (digital-to-analogue converters).

They are suitable for high-performance applications, such as wireless infrastructure equipment, medical imaging and industrial applications that require high speed, high channel density and good timing performance.

The six- to 12- additional clock channels reduce component count and board space while simplifying high-speed signal-chain design and lowering overall bill-of-materials costs.

The jitter and skew performance that the 12-channel ADCLK954 and the six-channel ADCLK946 LVPECL fan-out buffers deliver allows design engineers to achieve better SNR (signal-to-noise ratio) from an ADC or DAC.

The 4.8GHz ADCLK954 has two selectable differential inputs via the INSEL control pin.

Both inputs are equipped with 100-ohm on-chip termination resistors and may operate with either differential or single-ended clock sources.

The 12 LVDS/24 CMOS-channel ADCLK854 and six LVDS/12-CMOS-channel ADCLK846 provide high timing performance at 100-fs jitter.

All the clock buffers allow design engineers to benefit from the full resolution and performance of high-speed ADCs and DACs while maintaining low power of 12mW per channel at 100-MHz operation.

The ADCLK854 offers two selectable inputs and a sleep-mode feature.

The INSEL pin-state determines which input fans out to the outputs.

The sleep pin enables a sleep mode to power down the device.

The inputs accept various single-ended and differential logic levels, including LVPECL, LVDS, HSTL (high speed transceiver logic), CML (current-mode logic) and CMOS.